圖5顯示了一個(gè)例子，紅線是一個(gè)PCB上放置一些分立的去耦電容后得到的輸入阻抗。第一個(gè)諧振峰出現(xiàn)在600MHz到700MHz。在考慮了封裝結(jié)構(gòu)后，附加的封裝結(jié)構(gòu)的電感將諧振峰移到了大約450MHz處，見藍(lán)線。在包括了芯片電源供電系統(tǒng)后，芯片內(nèi)的去耦電容將那些高頻的諧振峰都去掉了，但同時(shí)卻引入了一個(gè)很弱的30MHz諧振峰，見綠線。這個(gè)30MHz的諧振在時(shí)域中會(huì)體現(xiàn)為高頻翻轉(zhuǎn)信號(hào)的中頻包絡(luò)上的一個(gè)電壓波谷。
芯片內(nèi)的去耦是很有效的，但代價(jià)卻是要用去芯片內(nèi)寶貴的空間和消耗更多的漏電流。將芯片內(nèi)的去耦電容挪到封裝結(jié)構(gòu)上也許是一個(gè)很好的折衷方案，但要求設(shè)計(jì)師擁有從芯片、封裝結(jié)構(gòu)到PCB的整個(gè)系統(tǒng)的知識(shí)。但通常，PCB的設(shè)計(jì)師無法獲得芯片和封裝結(jié)構(gòu)的設(shè)計(jì)數(shù)據(jù)以及相應(yīng)的仿真軟件包。對(duì)于集成電路設(shè)計(jì)師，他們通常不關(guān)心下端的封裝和電路板的設(shè)計(jì)。但顯然采用協(xié)同設(shè)計(jì)概念對(duì)整個(gè)系統(tǒng)、芯片-封裝-電路板的電源供電系統(tǒng)進(jìn)行優(yōu)化分析設(shè)計(jì)是將來發(fā)展的趨勢(shì)。一些走在電子設(shè)計(jì)前沿的公司事實(shí)上已經(jīng)這樣做了。
參考文獻(xiàn)
International Technology Roadmap for Semiconductors, 2005 Edition。
Raymond Y.Chen, IBIS Asia Summit, 2005
http://www.eda.org/pub/ibis/summits/dec05/chen.pdf
[3]Jiayuan Fang, Jin Zhao, The Power of Planes - Low Impedance Power Delivery over Broad Frequencies, Printed Circuit Design & Manufacturing Magazine, Sept.2003.
[4]Om, P.Mandhana, Jin Zhao, "Comparative Study on Effectiveness of On-Chip, On-Package and PCB Decoupling for Core Noise Reduction by Using Broadband Power Delivery Network Models, " 55th Electronic Components & Technology Conference, May 31-June 3, 2005，
[5]Jin Zhao, Michael Leins, "Evaluation and Elimination of PCB Edge Radiation Introduced by Core Switching Noise and I/O Simultaneous Switching Noise, " Technical Presentation at 2005 IEEE International Symposium on Electromagnetic Compatibility, 8-12 Aug, 2005, Chicago, Illinois
[6]Please find related information at www.Sigrity.com
[7]John Kane, "On-Chip Power Integrity, Including Package Effects，" SOC Central online articles, March
